1. Field of the Invention
The present invention relates to a stabilizing circuit for a phase locked loop. More specifically, the present invention relates to an improved stabilizing circuit for stabilizing a phase locked loop in a shortened time period when an input pulse signal is received.
2. Description of the Prior Art
A phase locked loop has been utilized in various types of electrical equipment. One application of a phase locked loop comprises a video disk player, wherein a phase locked loop is utilized for detecting a time base error, i.e. fluctuation of the time base of a horizontal synchronizing signal of a reproduced composite video signal for the purpose of correcting the time base error of the reproduced video signal. A scheme for correcting a time base error of a reproduced video signal responsive to fluctuation of the time base of a reproduced horizontal synchronizing signal has been fully described in United States patent application, Ser. No. 714,904, now U.S. Pat. No. 4,127,886, entitled "Jitter Correcting System in Video Reproducing Apparatus", filed Aug. 16, 1976 and assigned to the same assignee as the present invention.
A typical phase locked loop comprises an input pulse signal source for providing an input pulse signal of a given frequency, a voltage controlled signal generating means such as a voltage controlled oscillator for providing a signal of the frequency associated with a voltage control signal applied thereto, a phase comparator for comparing the phases of the input pulse signal and the output from the voltage controlled signal generating means, and a low pass filter for filtering the output of the phase comparator for providing a voltage control signal to the voltage controlled signal generating means. In one type of a phase locked loop, the output of the voltage controlled oscillator is directly applied to the phase comparator. On the other hand, in another type of a phase locked loop, the output of the voltage controlled oscillator is applied through a frequency divider to the phase comparator. In either case, the output level of the low pass filter becomes indefinite, if and when no input pulse signal is received from the input pulse signal source. In such a situation, a certain time period is required after a normal input pulse signal is received until the operation of the phase locked loop is stabilized. Such time period for stabilization of the phase locked loop is different depending on the circuit configuration of the phase locked loop. Thus, a certain type of a phase locked loop requires an undesirably prolonged time period for stabilization of the operation thereof. The above discussed problem is aggravated particularly in a case where an input pulse signal is often interrupted in the course of the operation of the equipment. For example, if a phase locked loop is employed in a video disk player for correcting a time base error of a reproduced video signal, the above discussed problem is aggravated by a provision of a pause scheme in the video disk player, which interrupts the operation of the phase locked loop and thus entails a prolonged time period for stabilization of a phase locked loop operation.
In order to describe in more detail the above discussed disadvantage, a starting operation of a typical phase locked loop will be described in the following. FIG. 1 shows a block diagram of such a typical conventional phase locked loop. FIG. 2 shows wave forms of the electrical signals at various portions in the FIG. 1 diagram. Referring to FIG. 1, the phase locked loop shown comprises a phase comparator connected to receive a normal input pulse signal through an input terminal 1 at one input thereof, a low pass filter 4 for filtering the output of the phase comparator 2 for providing a voltage control signal, and a voltage controlled oscillator 3 responsive to the voltage control signal from the low pass filter 4 for oscillating at a frequency associated with the voltage control signal, the output signal from the voltage controlled oscillator 3 being applied to another input of the phase comparator 2. The output of the voltage controlled oscillator 3 may be frequency divided by means of a frequency divider 5 interposed between the voltage controlled oscillator 3 and the phase comparator 2. With simultaneous reference to FIGS. 1 and 2, let it be assumed that a normal input pulse signal al as shown in FIG. 2 is received at the input terminal 1, starting at a time point t0. The input pulse signal al may be a horizontal synchronizing signal of a reproduced video signal obtained by a video disk player, for example. The phase comparator 2 is structured to provide a saw-tooth wave d1 responsive to the oscillation output signal from the voltage controlled oscillator 3. Therefore, starting from the time point t0, the saw-tooth wave signal is sampled by the pulse signal al, whereby an output signal of the wave form as shown as b1 in FIG. 2 is obtained from the phase comparator 2. The output signal b1 is applied to the low pass filter 4, whereby an output signal of the wave form as shown as c1 in FIG. 2 is obtained. The output of the low pass filter 4 before the normal input pulse signal is received at the time point t0 is in an indefinite level such as V0. At a time point t1 after the lapse of a given time period T since the input pulse signal comes to be received at the time point t0, an ultimately stabilized level V1 is reached. The above described time period T from the start of the normal input pulse signal to a time point where the phase locked loop operation is stabilized, i.e. the time period T=t1-t0, may be referred to as a pull-in time period and is dependent on the characteristic of the low pass filter and the difference between the level V0 before the normal input pulse signal is received and the level V1 after the phase locked loop operation is stabilized. More specifically, the larger the time constant of the low pass filter, or the larger the difference between the levels V0 and V1, the longer the pull-in time period of the phase locked loop.
FIG. 3 shows wave forms of the output of the low pass filter 4 in two different situations. Referring to FIG. 3, the wave form c3 shows an example in which the pull-in time period is prolonged when the indefinite level V0 is too small as at V01 with respect to the stabilized level V1, while the wave form c3' shows an example in which the pull-in time period is shortened when the indefinite level V0 is close to the stabilized level V1 as at V02. Thus, it would be appreciated that in order to shorten the pull-in time period the phase locked loop should be preferably structured such that the above described level difference may be eliminated when the characteristic of the low pass filter has been fixed. Nevertheless, when no input pulse signal is obtained at the input terminal 1, the voltage level of the output from the low pass filter 4 becomes indefinite. As a result, it is impossible to control the above described level difference between the indefinite level V0 and the stabilized level V1.
A prior art phase locked loop of interest to the present invention is seen in U.S. Pat. No. 3,059,187, issued Oct. 16, 1962 to R. M. JAFFE. The phase locked loop disclosed in the referenced patent comprises a phase comparator adapted to receive an input pulse signal and an output from a voltage controlled oscillator and a low pass filter for filtering the output of the phase comparator for providing a voltage control signal to the voltage controlled oscillator. The phase comparator is adapted to receive the input signal selectively from either an input pulse signal generator or a harmonic generator. More specifically, the phase comparator is adapted to be preliminarily supplied through a switching circuit with several harmonics from the harmonic generator so that a phase locked state is achieved with one of the harmonics but, whenever the input pulse signal is received, is adapted to be selectively supplied with the input pulse signal through the switching circuit which is switched responsive to the input pulse signal, while the phase locked state is maintained. Thus, the referenced patent is aimed to achieve a phase locked state in the phase locked loop even before the normal input signal is received, by providing several harmonics to the phase comparator. This, however, necessitates a harmonic generator of a complicated circuit configuration. Thus, it is desired that an improved stabilizing circuit for a phase locked loop of a simplified circuit configuration is provided. The present invention acheives that purpose.